A typical memory unit may be viewed as having a plurality of storage cells (or simply, “cells”). The memory unit may be randomly accessed according to address signals. In the randomly accessible memory unit, associated with each cell is a unique address that identifies the location of a particular storage cell. Each storage cell can have the capacity to store “n” bits (where n is an integer greater than or equal to one). The n bits may be collectively referred to as a word of data.
Often, a memory unit is written to by: 1) providing a word of data to be written into the memory unit on a data bus; 2) providing an address that defines which storage cell will store the word of data; and 3) presenting a signal to the memory unit that effectively indicates the word of data on the data bus is to be written into the memory unit, such as a write enable (WE) control signal.
Often, a memory unit is read from by: 1) providing an address that defines which cell a word of data will be read from; and 2) presenting a signal to the memory unit that effectively indicates a word of data is to be read from the memory unit, such as a read enable (RE) control signal. The word of data retrieved from the memory unit is presented at the data output bus.
Alternatively, the cell identification in a write operation could be according to a time sequence based addressing, such as in a shift register. Or, it could be addressed using a mix of address and a time based sequence.
For example, some types of memory units are designed such that the memory cells are accessed according to predetermined sequences, such as a first-in first-out (FIFO) memory, a shift register look up table (SRL), etc. Words of data are written into the cells of such a memory unit in a predetermined fashion. The memory unit may be written to without supplied address. Data words are written into the corresponding memory cells based on the time sequence of write operations. The words of data may be read in a predetermined fashion, or be read randomly with a supplied address.
A commercial example that uses a mix of address and time based read/write is the Xilinx Virtex SRL primitive that is written into like a shift register and is read from like a RAM.
A memory unit may receive addresses for read and write from separate address buses or from the same address bus. A memory unit may receive data and output data on separate unidirectional buses, or on a bi-directional bus. In some embodiments, a single control line may be toggled between the read enable (RE) signal and the write enable (WE) signal, or be used to signal both the read and write operations when asserted (e.g., when the control signal line is having a particular value, such as one).
A memory unit can be used to implement a number of storage related devices such as a random access memory (RAM), a first-in-first-out (FIFO) queue (e.g., by appropriately controlling the address values of the memory unit such that a FIFO queue is emulated with the memory unit), a content addressable memory (CAM), a shift register, etc.
Some memory units as being offered to designers to implement their circuit designs, however, may not have a reset function. A reset function effectively “clears” the memory unit's cell word values to some “reset” value (e.g., an n-bit wide value of “0”, or other predetermined values which may be dependent on the locations of the cells in a memory unit).
Often, the integration of circuitry for resetting the cell word values of the memory unit is too expensive and/or complicated to implement. For example, according to one approach, in order to implement a resettable memory, each n wide storage cell is implemented with resettable flip-flops that are individually accessed via complicated multiplexing and control circuitry. Here, the use of resettable flip-flops to implement each n wide storage cell (as well as the complicated multiplexing and control circuitry) can result in a resettable memory unit having noticeably slower performance (and that consumes more silicon surface area) than a memory unit that does not have resettable storage cells.
For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.